1. Field of the Invention
The present invention relates to an adder circuit apparatus in which serial plural-digit full adders are arranged in blocks, more particularly, it relates to an adder circuit apparatus including a Manchester-carry-chain circuit with a carry-look-ahead circuit as a carry signal propagation circuit.
2. Description of Related Art
A conventional full adder and a Manchester-carry-chain circuit are described, for example, on pages 324, 325, in "PRINCIPLES OF CMOS VLSI DESIGN" by Neil H. E. Weste and Kamran Eshraghian, published by Addison-Wesley Publishing Corp. FIGS. 1 and 2 illustrate circuit diagrams showing the configuration of the prior art full adder and Manchester-carry-chain circuit described in the aforesaid book. In FIG. 1, an i th bit addend input signal A.sub.i and an augend input signal B.sub.i are given to a NAND circuit 1.sub.a and an NOR circuit 2.sub.a respectively. An output signal of the NAND circuit 1.sub.a is given to one end of a NAND circuit 1.sub.b and is outputted as a carry generation signal G.sub.i via an inverter 3.sub.e. An output signal of the NOR circuit 2.sub.a is given to the other end of the NAND circuit 1.sub.b via an inverter 3.sub.f. An output signal of the NAND circuit 1.sub.b is outputted as a carry propagation signal P.sub.i via an inverter 3.sub.g and is given to one end of an exclusive (hereinafter referred to as Ex) NOR circuit 4. An i-1 th bit inversion carry output signal (hereinafter referred to as a carry signal) C.sub.i-1 is given to the other end of the ExNOR circuit 4, of which output signal is outputted as an i th bit sum output signal S.sub.i.
In FIG. 2, numeral 7 indicates a 4-bit Manchester-carry-chain circuit, which comprises five P channel transistor (hereinafter referred to as PchTR) 5.sub.a0, 5.sub.a1 . . . 5.sub.a4 whose sources are connected to a power supply, five N channel transistors (hereinafter referred to as NchTR) 6.sub.a0, 6.sub.a1 . . . 6.sub.a4 whose drains are connected to each drain of said PchTRs 5.sub.a0, 5.sub.a1 . . . , five NchTRs 6.sub.b0, 6.sub.b1 . . . 6.sub.b4 whose drains are connected to the sources of said NchTRs 6.sub.a0, 6.sub.a1 . . . 6.sub.a4 respectively and whose sources are earthed, four NchTRs 6.sub.g1, 6.sub.g2, 6.sub.g3, 6.sub.g4 whose sources are connected to intermediate nodes between the PchTRs 5.sub.a0 .about.5.sub.a3 and the NchTRs 6.sub.a0 .about.6.sub.a3, and whose drains are connected to intermediate nodes between the PchTRs 5.sub.a1 .about.5.sub.a4 and the NchTRs 6.sub.a1 .about.6.sub.a4 and an inverter 3.sub.a1 which outputs a 4-bit carry signal C.sub.4. There are given a clock signal CLK to the gates of the PchTRs 5.sub.a0, 5.sub.a1 . . . and NchTRs 6.sub.b0, 6.sub.b1 . . . , a first carry signal C.sub.0 to the gate of the NchTR 6.sub.a0, and carry generation signals G.sub.1, G.sub.2 . . . for each bit to the gates of the NchTRs 6.sub.a1, 6.sub.a2 . . . , respectively. Carry propagation signals P.sub.1, P.sub.2 . . . for each bit are given to the gates of the NchTRs 6.sub.g1, 6.sub.g2 . . . . The intermediate node between the PchTR 5.sub.a0 and NchTR 6.sub.a0 and that between the PchTR 5.sub.a4 and NchTR 6.sub.a4 are connected via an NchTR 6.sub.L1.
Numeral 9 denotes a carry-look-ahead circuit, which comprises, a clocked AND circuit 8 provided in every block each consisting of 4 bits, and in which a PchTR 5.sub.b1 and the NchTRs 6.sub.c1, 6.sub.c2, 6.sub.c3, 6.sub.c4 connected to a power supply at their sources and an NchTR 6.sub.d1 earthed at its source are connected in series, and an inverter 3.sub.b1 is connected to an intermediate node between the PchTR 5.sub.b1 and NchTR 6.sub.c1, and the aforesaid NchTR 6.sub.L1. Output of the inverter 3.sub.b1 is given to a gate of the NchTR 6.sub.L1, so is the clock signal CLK to a gate of the NchTR 6.sub.d1. To gates of the NchTRs 6.sub.c1, 6.sub.c2, 6.sub.c3, 6.sub.c4, carry propagation signals P.sub.1, P.sub.2, P.sub.3, P.sub.4 for each bit are given separately.
In the following, the operation of the conventional adder circuit thus constructed will be described. Table 1 below shows a truth table of the full adder shown in FIG. 1.
TABLE 1 ______________________________________ A.sub.i B.sub.i G.sub.i P.sub.i ##STR1## S.sub.i ______________________________________ 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 1 1 0 0 1 1 0 ______________________________________
As it will be apparent from the Table 1, a carry generation signal G.sub.i becomes "1" when both the addend input signal A.sub.i and the augend input signal B.sub.i are "1". Also, a carry propagation signal P.sub.i becomes "1" when the addend input signal A.sub.i and the augend input signal B.sub.i show the different values.
Meanwhile, in FIG. 2, because the PchTRs 5.sub.a0 .about.5.sub.a4 and 5.sub.b1 are ON and the NchTRs 6.sub.b0 .about.6.sub.b4 and 6.sub.d1 are OFF when the clock signal CLK is "0", the inversion carry signal C.sub.i of each bit becomes "1" respectively by a power supply voltage.
When the clock signal CLK becomes "1" and the carry generation signal G.sub.i is "1", the inversion carry signal C.sub.i becomes "0" and the carry signal C.sub.i is generated. At that time, if the carry propagation signal P.sub.i is "1", the NchTR 6.sub.gi to which the carry propagation signal P.sub.i is inputted is turned on, and the (i-1)th bit inversion carry signal C.sub.i-1 is propagated as the i th bit inversion carry signal C.sub.i. This inversion carry signal C.sub.i is added to the addend input signal A.sub.i+1 and the augend input signal B.sub.i+1 in the full adder of the (i+1)th bit, thereby a sum output signal S.sub.i+1 is obtained.
While, when the clock signal CLK becomes "1" and all of the carry propagation signal P.sub.i are "1", the output signal from the inverter 3.sub.b1 in the clocked AND circuit 8 of the carry-look-ahead circuit 9 becomes "1" and the NchTR 6.sub.L1 is turned on, thereby the first inversion carry signal C.sub.0 of the Manchester-carry-chain circuit 7 is propagated directly as the 4th bit inversion carry signal C.sub.4.
A maximum delay path with the longest propagation time of carry signal of the circuit shown in FIG. 2 will now be considered.
Firstly, when the carry signal C.sub.0 and the carry propagation signals P.sub.1 .about.P.sub.4 are "1", though the first inversion carry signal C.sub.0 is propagated as the inversion carry signal C.sub.4 via the 4-step NchTRs 6.sub.g1 .about.6.sub.g4, at this time the NchTR 6.sub.L1 is turned on by the carry-look-ahead circuit 9, allowing it to propagate also via the 1-step NchTR 6.sub.L1, then, this will not be the maximum delay path.
When the carry generation signal G.sub.1 and the carry propagation signals P.sub.2 .about.P.sub.4 are "1", however, since the inversion carry signal C.sub.1 is propagated via the 3-step NchTRs 6.sub.g2 .about.6.sub.g4, this will be the maximum delay path of the Manchester-carry-chain circuit 7.
Next will be described a maximum delay path of the carry signal when the adder circuits are aligned in plural steps as shown in FIG. 2.
FIG. 3 is a circuit diagram showing the configuration of a conventional 32-bit adder circuit, in which eight 4-bit Manchester-carry-chain circuits shown in FIG. 2 are connected in series. Here j indicates a block, 6.sub.Lj denotes an NchTR in the j th block carry-look-ahead circuit 9 from the low-order, C.sub.i designates an i th bit carry signal, so does C.sub.i an i th bit inversion carry signal.
When the carry signal generated in the low-order is propagated as the top-order carry signal, the number of NchTRs interposed therebetween increases to become a maximum delay path.
The maximum delay path in the adder circuit constructed as shown in FIG. 3 is attained by propagating the carry signal C.sub.1 generated in the first bit as the 32nd bit carry signal C.sub.32. That is, it is the case when the carry generation signal G.sub.1 and the carry propagation signals P.sub.2 .about.P.sub.22 are "1". In this case, the inversion carry signal C.sub.1 is propagated as the carry signal C.sub.4 via the 3-step NchTRs 6.sub.g2 .about.6.sub.G4 and a 1-step inverter 3.sub.a, and then is propagated as the carry signal C.sub.32 via the 7-step NchTRs 6.sub.L2 .about.6.sub.L8 and 14-step inverters 3.sub.a, 3.sub.b . . . of the carry-look-ahead circuits 9, 9 . . . present at intervals of four bits. Thus, when the maximum delay path is passed, the carry signal C.sub.1 is propagated via the total of 10-step NchTRs and 15-step inverters.
In such a prior art adder circuit as described above, when a low-order digit carry signal is propagated directly to the high-order digit, it has to pass all of the carry-look-ahead circuit gates in the higher order than the propagation starting digit, thus, the propagation time of the carry signal is considerably delayed to hinder the high-speed operation.